1. Field of the Invention
The present invention relates generally to fabrication of metal oxide semiconductor field effect transistors (MOSFETs), and, more particularly, to the measurement of MOSFET characteristics.
2. Related Technology
MOSFETs are a common component of integrated circuits (ICs). FIG. 1 shows a cross sectional view of a conventional MOSFET. The MOSFET is fabricated on a silicon substrate 10 within an active region bounded by shallow trench isolations 12 that electrically isolate the active region of the MOSFET from other IC components fabricated on the substrate 10.
The MOSFET is comprised of deep source and drain regions 14 having shallow source and drain regions 16 extending therefrom toward a channel region 18. The use of shallow source and drain extensions 16 rather than deep source and drain regions near the ends of the channel 18 helps to reduce short channel effects.
A gate 20 is separated from the channel region 18 by a thin gate insulator 22 such as silicon oxide or oxide-nitride-oxide (ONO). The gate is surrounded by first 24 and second 26 spacers that align the locations of the shallow source and drain extensions 16 and the deep source and drain regions 18 during their implantation.
Silicides 28, 30 are formed on the source and drain regions 14 and the gate 20 to provide ohmic contacts. The silicides typically comprise cobalt (Co) or nickel (Ni).
One option for increasing the performance of MOSFETs is to enhance the carrier mobility of the MOSFET semiconductor material so as to reduce resistance and power consumption and to increase drive current, frequency response and operating speed. A method of enhancing carrier mobility that has become a focus of attention is the use of silicon material to which a tensile strain is applied. xe2x80x9cStrainedxe2x80x9d silicon may be formed by growing a layer of silicon on a silicon germanium substrate. The silicon germanium lattice is more widely spaced on average than a pure silicon lattice because of the presence of the larger germanium atoms in the lattice. Because the atoms of the silicon lattice align with the more widely spread silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. The amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the silicon germanium lattice.
The tensile strain applied to the silicon lattice increases carrier mobility. Relaxed silicon has six equal valence bands. The application of tensile strain to the silicon lattice causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. Due to quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons encounter less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, offering a potential increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
An example of a MOSFET using a strained silicon layer is shown in FIG. 2. The MOSFET is fabricated on a substrate comprising a silicon germanium layer 32 grown on a silicon layer 10. An epitaxial layer of strained silicon 34 is grown on the silicon germanium layer 32. The MOSFET uses conventional MOSFET structures including deep source and drain regions 14, shallow source and drain extensions 16, a gate oxide layer 22, a gate 20 surrounded by spacers 24, 26, source and drain silicides 28, a gate silicide 30, and shallow trench isolations 12. The channel region of the MOSFET includes the strained silicon material, which provides enhanced carrier mobility between the source and drain.
The substrate in which a MOSFET is formed is lightly doped with a dopant of a first conductivity, and the source and drain regions of the MOSFET are heavily doped with a dopant of the opposite conductivity. For example, the substrate may be lightly doped with a p-type dopant, while the source and drain regions may be heavily doped with an n-type dopant. As a result, the channel region between the source and drain regions has very few n-type carriers, and there is effectively an open circuit between the source and drain regions. The gate of the MOSFET acts as a capacitor, such that when a gate voltage VGS of appropriate polarity is applied to the gate, carriers of the opposite conductivity are drawn from the substrate to create a thin xe2x80x9cinversion layerxe2x80x9d in the channel region. The presence of the inversion layer enables current flow between the source and drain. This type of MOSFET is referred to as an enhancement-only type MOSFET, since the application of voltage to the gate is only capable of enhancing the conductivity between the source and drain. The amount of current that can flow between the source and drain depends on the availability of carriers in the channel region, and therefore is controlled by the gate voltage VGS. The minimum gate voltage VGS required to create an inversion layer in the channel is referred to as the threshold voltage VGS(th).
The use of heavily doped source and drain regions in an oppositely doped substrate creates depletion regions at the junctions of the source and drain regions with the oppositely doped substrate. The depletion regions provide electrical isolation of the MOSFET from other devices formed in the substrate.
MOSFETs are typically characterized by a set of drain curves as shown in FIG. 3. The drain curves of FIG. 3 show the effect on the drain current ID of changes in the source/drain voltage VDS for various gate voltages VGS. As shown by the drain curves, the drain current ID increases in an approximately linear manner until a saturation point is reached and all available carriers are being used for conduction. Beyond the saturation point, further increases in source/drain voltage VDS produce negligible increases in drain current ID. The saturation current increases with increasing gate voltage VGS because an increase in gate voltage makes more carriers available in the inversion layer.
As MOSFETs become smaller, it becomes more important to accurately characterize the resistance of the source and drain regions. Conventionally, the source and drain resistances are not measured individually. Rather, the aggregate source and drain resistance RDS is extrapolated from the drain curves. As seen in FIG. 3, the aggregate source and drain resistance RDS is approximately represented by the slope of the pre-saturation portions of the drain curves. However, at small device dimensions, variations in the individual source and drain resistances can have pronounced effects on device performance, and it cannot be assumed that the source and drain resistances are equal. As a result, the conventional source/drain resistance measurement is inadequate because it does not determine individual values for the source and drain resistances.
Embodiments of the present invention pertain to a technique for measuring the individual source and drain resistances of a MOSFET.
In accordance with an embodiment of the invention, the source resistance is determined by grounding the source and applying a voltage to the substrate to force a current Isub-S through the source. If the gate and drain are allowed to float while current is forced through the source, no current flows between the source and drain, and as a result any voltage VDS detected at the drain is the product of the forced current Isub-S and the source resistance RS. Accordingly, the source resistance RS is determined to be the drain voltage VDS divided by the forced current Isub-S.
In accordance with one embodiment of the invention, the source or drain resistance of a MOSFET is measured individually. For purposes of this summary the measurement of source resistance will be described, however drain resistance may be measured by the same process. Initially the source is grounded while the gate and the drain are allowed to float. A current is then applied to the substrate in which the source and drain are formed. Voltage is measured at the drain while the current applied to the substrate flows through the source to ground. The resistance of the source is then determined from the current applied to the substrate and the voltage measured at the drain. Ideally several voltage measurements are made at several different currents, and the source resistance is determined to be an average of the resistances indicated by each of the individual measurements. The measurements should exclude any measurements made during a transient flyback condition. The current applied to the substrate during the measurements should be produced by application to the substrate of a voltage of sufficient magnitude to avoid creation of a transient flyback condition. The process in preferably automated.